A field programmable device (or a so-called "field programmable gate array") is a versatile integrated circuit chip, the internal circuitry of which may be configured by an individual user to realize a user-specific circuit. To configure a field programmable device, the user configures an on-chip interconnect structure of the field programmable device so that selected inputs and selected outputs of selected on-chip logic components are connected together in such a way that the resulting circuit is the user-specific circuit desired by the user.
FIG. 1A-1B is a top down simplified diagram illustrating a corner portion of a field programmable device. Three vertical routing channels A-C and three horizontal routing channels D-F separate nine universal logic modules M1-M9. These nine logic modules are arranged in a three-by-three matrix. Each logic module may, for example, comprise logic components such as digital logic gates, digital sequential logic circuitry, and other circuitry.
In the vertical dimension, routing channel A, for example, comprises two tracks T1 and T2. Track T1, for example, comprises of wires W1, W2, W3, and W4. A transistor P1, called a pass transistor, is connected between wires W1 and W2. A second pass transistor P2 is connected between wires W2 and W3. A third pass transistor P3 is connected between wires W3 and W4. The other illustrated wires W5-W24 and the other illustrated pass transistors P4-P18 of the vertical tracks of FIG. 1A-1B are similarly numbered.
In the horizontal dimension, routing channel F, for example, comprises two tracks T3 an T4. Track T3, for example, comprises wires W25, W26, and W27. A pass transistor P19 is connected between wires W25 and W26. A pass transistor P20 is connected between wires W26 and W27. The other illustrated wires W28-W42 and the other illustrated pass transistors P21-P30 of the horizontal tracks of FIG. 1A-1B are similarly numbered.
Each of the small circles in FIG. 1A-1B represents an unprogrammed connection element referred to as a programmable "antifuse". In contrast to typical fuses used in programmable read-only memory (PROM) devices which are normally conductive and are "blown" to be nonconductive, antifuses are normally nonconductive and can be "programmed" to be conductive.
Due to the large number of antifuses in the structure represented by FIG. 1A-1B, only certain of the antifuses are supplied with reference numerals. Some of the antifuses, called "cross antifuses", are located substantially at the cross points of horizontal and vertical wires. These cross antifuses can be programmed to connect a horizontal wire with a vertical wire.
FIG. 2 is a cross sectional view of one possible embodiment of a cross antifuse. Cross antifuse 20 comprises a thin dielectric body layer 21 and a layer of diffusible conductive material 22 sandwiched between horizontal wire 23 and vertical wire 25 so that a first surface portion 26 of the antifuse contacts vertical wire 25 and so that a second surface portion contacts horizontal wire 23. The horizontal wire 23 may, for example, be located on a first metallization layer of the programmable device whereas the vertical wire 25 may be located on a second metallization layer of the programmable device. An insulating layer 28 may be disposed between the first metallization layer and the second metallization layer so that the cross antifuse forms a via-like structure from the vertical wire 25 down to the horizontal wire 23. In its unprogrammed state, horizontal wire 23 is insulated from vertical wire 25 by dielectric body layer 21. In its programmed state, a conductive path 29 is formed through body layer 21 so that horizontal wire 23 and vertical wire 25 are substantially electrically connected. One such cross antifuse L1 is disposed between and vertical wire W1 and a horizontal wire W27 in the circuit of FIG. 1A-1B.
Other of the antifuses, called "pass antifuses", may be programmed to electrically connect the source and drain of a pass transistor together so that two adjacent wires in a single track are connected together in series independent of the state of the pass transistor. One such pass antifuse which may be programmed to connect horizontal wire W26 to horizontal wire W27 is pass antifuse L2.
The field programmable device of FIG. 1A-1B also has input/output circuitry for interfacing the user-defined circuit of the interconnected logic modules to other circuitry off-chip. A signal originating from off-chip may, for example, be input onto vertical wire W8 via I/O pad A1 and input I/O buffer A2. A signal on vertical wire W4 generated on-chip may, for example, be output to circuitry off-chip via output I/O buffer A3 and output I/O pad A4.
Each of the modules M1-M9 has digital signal input wires and digital signal output wires. Module M1, for example, has a single digital signal input wire W43 entering module M1 from the left and a single digital signal output wire W44 exiting module M1 to the left. Module M4 has an input wire W45 and an output wire W46. Although the modules in the device of FIGS. 1A-1B each have only one input wire and one output wire, each module of an actual device may have a great number of digital signal wires. To connect these digital signal input and output wires to the rest of the interconnect circuitry, cross antifuses are provided on each digital signal input wire and each digital signal output wire where the input or output wire crosses a vertical wire. Input wire W43, for example, has two cross antifuses L18 and L19. Input wire W45 has two cross antifuses L20 and L21. Transistors, such as transistor T1, are provided to connect adjacent ones of these digital signal wires together during programming of cross antifuses.
Although FIG. 1A-1B shows wires W1, W5, W9, W13, W17 and W21 as single wires connected between I/O buffers and cross antifuses, additional rows of logic modules and associated horizontal routing channels are disposed between the bottom row of cross antifuses and the bottom row of I/O buffers and I/O pads. Similarly, additional columns of logic modules and associated vertical routing channels are disposed between the leftmost column of cross antifuses and the leftmost column of I/O buffers and I/O pads. The structure of FIG. 1A-1B is therefore a simplified representation of an upper right corner portion of a larger field programmable device.
To realize a desired circuit from the unprogrammed structure of FIG. 1A-1B, selected antifuses in the structure are programmed so that various of the wires W1-W60 are connected together to form an interconnect net from one specific output of a specific digital logic component in a module to one or more specific inputs of other specific digital logic components in another module. The antifuses in FIG. 1A-1B are programmed when a high programming voltage (Vpp) having a magnitude greater that the normal operating voltage supply of the programmable device is placed across the antifuse. If, for example, the normal operating voltage is approximately 5 volts plus or minus 10 percent, placing a programming voltage Vpp of having a magnitude greater than approximately 11 volts across an antifuse will cause the antifuse to become to become conductive. Unprogrammed antifuses may have a conductivity of approximately 1-50 gigaohms or more whereas programmed antifuses may have a conductivity of approximately 50 ohms or less.
FIG. 3 shows the programming of a pass antifuse L3 in the field programmable device of FIG. 1A-1B. In the circuit shown in FIG. 1A-1B, each end of track T6 has a programming driver. Programming driver PD1 is connected to vertical wire W13 and programming driver PD2 is connected to vertical wire W16. These programming drivers have tri-state outputs so that they can be disconnected from wires W13 and W16 during normal circuit operation. During the programming of antifuses, however, these programming drivers may be controlled to output a programming voltage (Vpp), or may be controlled to output a ground voltage.
In the example shown in FIG. 3, pass antifuse L3 is to be programmed. Pass transistors P12 and P11 are turned on whereas pass transistor P10 is not turned on. Programming driver PD2 is controlled to drive vertical wire W16 with the programming voltage Vpp and programming driver PD1 is controlled to drive wire W13 with a ground voltage. Because pass transistors P12 and P11 are turned on and pass transistor P10 is turned off, programming voltage Vpp propagates to wire W15 and then to wire W14. A significant portion of programming voltage Vpp is therefore dropped between wire W14 and wire W13 across pass antifuse L3. Consequently, antifuse L3 is programmed. Antifuses L4 and L5 are not programmed because conductive pass transistors P11 and P12 prevent a large voltage from developing across antifuses L4 and L5 respectively. Antifuse L3, on the other hand, is programmed because pass transistor P10 is not conductive and does not prevent the programming voltage from developing across antifuse L3. The path from Vpp to antifuse L3 to be programmed and from antifuse L3 to ground is called a programming path. This programming path only comprises two branches. One branch extends from programming driver PD2 to a first surface portion of the antifuse to be programmed L3. A second branch extends from a second portion of the antifuse to be programmed L3 to programming driver PD1. Programming of antifuse L3 causes the first surface portion of antifuse L3 to be permanently electrically connected to the second surface portion of antifuse L3.
FIG. 4 shows the programming of cross antifuse L6 in the field programmable device of FIG. 1A-1B. In this case, both programming drivers PD1 and PD2 may be set to output the programming voltage Vpp. Because pass transistors P10-P12 are turned on, vertical wire W14 is driven with the programming voltage Vpp. To create a voltage drop across cross antifuse L6, horizontal wire W32 is driven to the ground voltage. Accordingly, programming driver PD4 is set to drive horizontal wire W33 to ground and programming driver PD3 is set to drive horizontal wire W31 to ground. By turning pass transistors P24 and P23 on, horizontal wire W32 is driven with the ground voltage, thereby placing a significant portion of programming voltage Vpp across cross antifuse L6 and thereby programming cross antifuse L6.
The programming path shown in FIG. 4 comprises four programming branches. A first programming branch extends from programming driver PD2, through wire W16, through conductive transistor P12, through wire W15, through conductive transistor P11, through wire W14, and to a first surface portion of the antifuse L6 to be programmed. A second programming branch extends from programming driver PD1, through wire W13, through conductive transistor P10, through wire W14 and to the first surface portion of antifuse L6 to be programmed. A third programming branch extends from programming driver PD3, through wire W31, through pass transistor P23, through wire W3,2 and to a second surface portion of antifuse L6 to be programmed. A fourth programming branch extends from programming driver PD4, through wire W33, through pass transistor P24, through wire W32, and to the second surface portion of antifuse L6 to be programmed. Before antifuse L6 is programmed, the first surface portion of antifuse L6 is insulated from the second surface portion of antifuse L6. After programming the first surface portion of antifuse L6 is substantially electrically connected to the second surface portion of antifuse L6.
Although the above described programming of cross antifuses and pass antifuses may be satisfactory in certain applications, the resistances of the resulting programmed antifuses may often be higher than desired. In the design of large high speed circuits, for example, the resistance of a net determines in part the speed at which a given driver circuit can drive the net from one digital logic voltage level to the other digital logic voltage level. The resistance of the net therefore in part determines the switching speed of the circuit. When long nets are made by connecting multiple wires together using multiple connecting antifuses, the series resistances of the multiple antifuses of the net add together to result in a significant total net resistance. Accordingly, the switching speed of the net is degraded.
In some types of recently developed programmable antifuses, the resistance of a resulting programmed antifuse is a function of the magnitude of the programming current which flows through the antifuse from the first surface portion of the antifuse to the second surface portion of the antifuse during programming and also the time that this programming current flows through the antifuse during programming. In general, an antifuse programmed by dropping the full programming voltage Vpp between the first and second surface portions of the antifuse will have a lower resultant programmed resistance than that same antifuse programmed by dropping a smaller voltage between the first and second surface portions.
In the circuit of FIG. 3, the full programming voltage Vpp is not dropped across antifuse L3 to be programmed. A resistance exists in the two branch programming path from Vpp to antifuse L3 and from antifuse L3 to ground. This resistance causes a voltage drop which reduces the voltage dropped across antifuse L3 and reduces the current flowing through antifuse L3 during programming. The bulk of this programming path resistance is due to the on-resistance of pass transistors P11 and P12. Similarly in the circuit of FIG. 4, although a larger portion of programming voltage Vpp is dropped across cross antifuse L6 during programming, the voltage drop across cross antifuse L6 is still less than Vpp. A resistance does exists in the four branch programming path from Vpp to antifuse L6 and from antifuse L6 to ground. This programming path resistance therefore serves to reduce the magnitude of the voltage dropped across the antifuse L6 during programming.